The invention relates to rail-to-rail class AB output stages, especially for rail-to-rail operational amplifiers, and more particularly to rail-to-rail class AB output stages which are both capable of operation with very low power supply voltages and also are sufficiently faster than operational amplifier front end circuitry to avoid non-linear distortion of the output signals.
The closest prior art includes U.S. Pat. No. 5,311,145 entitled xe2x80x9cCombination Driver-Summing Circuit for Rail-to-Rail Differential Amplifierxe2x80x9d issued May 10, 1994 to Huijsing et al. and incorporated herein by reference, U.S. Pat. No. 4,570,128 (Monticelli), the article xe2x80x9cCompact Low-Voltage Power-Efficient Cells for VLSIxe2x80x9d, by K. Langen and J. Huijsing, IIIE Journal of Solid State Circuits, Volume 33, No. 10, pp. 1482-1496, the article xe2x80x9cRail-to-Rail Constant-Gm Input Stage and Class AB Output Stage for Low-Voltage CMOS Op Ampsxe2x80x9d by R. Wassenaar et al., Analog Integrated Circuits and Signal Processing, 1996, No. 6, pp. 121-123, and the article xe2x80x9cDesign Aspects of Rail-to-Rail CMOS OpAmpxe2x80x9d, by Gierkink, Holzmann, Wiegerink, and Wassenaar, proceedings of the 1st VLSI Workshop, May 6-8, 1997, Columbus, Ohio, pp. 23-28.
Monticelli patent 4,570,128 discloses a rail-to-rail class AB output stage. FIG. 1 of prior art patent 5,311,145 discloses an operational amplifier capable of xe2x80x9crail-to-rail operationxe2x80x9d. The operational amplifier includes a differential amplifier input stage having two pairs of differentially coupled input MOSFETs, one with a tail current from the positive rail (i.e., supply voltage conductor) and the other with a tail current into the negative rail. A class A-B driver/output stage of the operational amplifier is coupled to a pair of folded cascode transistors to produce an output signal which is operative over nearly the full rail-to-rail supply voltage range. The article by Langen and Huijsing mainly discloses the circuitry in Patent 5,311,145 in more detail. The paper by Gierkink, Holzmann, Wiegerink, and Wassenaar discloses use of a gain boost amplifier with a cascode connection and a differential amplifier. The circuitry disclosed in this reference is very complex, and needs a large compensation capacitor. There is a need to provide a simpler circuit. The rail-to-rail class AB output stages disclosed in the foregoing articles all include multiple stage feedback circuits that produce three inversions and cause the feedback circuits to be substantially slower than the prior operational amplifier stages. The slowness causes both signal instability problems and non-linear signal distortion in the operational amplifier.
The circuit described in Huijsing et al. patent 5,311,145 is a two-stage circuit that does not have the capability of operating at a rail-to-rail supply voltage of less than approximately 2.2 volts. The gain of this circuit is too low for many applications. The speed-power figure of merit for the circuits described in patent 5,311,145 is much lower than desirable at lower rail-to-rail supply voltages. The circuit described in Monticelli patent 4,570,128 also has the shortcoming that a CMOS implementation thereof is not capable of rail-to-rail operation at power supply voltages less than approximately 2.2 volts.
Accordingly, it is an object of the invention to provide a class AB output stage suitable for use in an operational amplifier having at least two stages of front end circuitry, wherein the class AB output stage is fast enough to avoid non-linear distortion of the output signal produced by the operational amplifier.
It is another object of the invention to provide a rail-to-rail class AB output stage that is suitable for use in an operational amplifier having at least two stages of front end circuitry, wherein the class AB output stage is fast enough to avoid non-linear distortion of the output signal produced by the operational amplifier.
It is another object of the invention to provide a rail-to-rail class AB output stage that is suitable for use in an operational amplifier having at least two stages of front end circuitry, wherein the class AB output stage is fast enough to avoid non-linear distortion of the output signal produced by the operational amplifier and is also capable of operating at a power supply voltage as low as 1.8 volts.
It is another object of the invention to provide an improved amplifying stage for a rail-to-rail class AB output stage.
Briefly described, and in accordance with one embodiment thereof, the invention provides a class AB output stage including an amplifying stage, a pull-up transistor (14), a pull-down transistor (12), and first and second feedback circuits, the amplifying circuit it adapted to produce first (9) and second (10) output signals which incrementally increase and decrease in response to an incremental increase and decrease, respectively, of a first input signal (Iin1), and which also incrementally increase and decrease in response to an incremental increase and decrease, respectively, of a second input signal (Iin2). The pull-up transistor (14) has a source coupled to a first supply voltage conductor (V+), a gate coupled to receive the second signal (10), and a drain coupled to an output terminal (15). The pull-down transistor (12) has a source coupled to a second supply voltage conductor (GND), a gate coupled to receive the first signal (9), and a drain coupled to the output terminal (15). The first feedback circuit includes a first current sensing transistor (11) having a gate and source connected to the gate and source, respectively, of the pull-down transistor (12) and a drain coupled to a first control input (7) of the amplifying stage and operative to increase the gate voltage of the first current sensing transistor (11) only until its drain current increases to a first predetermined value representative of a minimum desired quiescent current in the pull-down transistor (12). The second feedback circuit includes a second current sensing transistor (13) having a gate and source connected to the gate and source, respectively, of the pull-up transistor (14), and a drain coupled to a second control input (18) of the amplifying stage and operative to decrease the gate voltage of the second current sensing transistor (13) only until its drain current increases to a second predetermined value representative of a minimum desired quiescent current in the pull-up transistor.
The first feedback circuit includes a first limiting circuit (34 or 45,44,41) adapted to prevent feedback from the drain of the first current sensing transistor (11) to the first control terminal (7) if the drain current of the first current sensing transistor (11) exceeds the first predetermined value, and wherein the second feedback circuit includes a second limiting circuit (31 or 43,42,40) adapted to prevent feedback from the drain of the second current sensing transistor (13) to the second control terminal (18) if the drain currents of the second current sensing transistor (13) exceeds the second predetermined value.
In the described embodiments, the amplifying stage (22) includes first (3), second (4), third (16), and fourth (17) transistors, first (5) and second (20) constant current sources, and first (8) and second (25) V/I converters, the sources of the first and second transistors being connected to the first signal input conductor (2) and the first constant current source (5). The sources of the third and fourth transistors are connected to the second signal input conductor (3) and the second constant current source in (20), the drain of the third transistor (16) is connected by the first output conductor (9) to the drain of the first transistor (3), and the drain of the fourth transistor (17) is connected by the second output conductor (10) to the drain of the second transistor (4). The gates of the first, second, third, and fourth transistors are connected to the first reference voltage (6), the first control conductor (7), the second control conductor (18), and the second the reference voltage (19), respectively. The first V/I converter (8) is connected between the gates of the first (3) and second (4) transistors. The second V/I converter (25) is connected between the gates of the third (16) and fourth (17) transistors. The pull-up transistor (14), first transistor (3), and second transistor (4) are P-channel MOSFETs, and the pull-down transistor (12), third transistor (16) and fourth transistor (17) are N-channel MOSFETs. The first V/I converter (8) includes a differential stage including first (8A) and second (8B) P-channel input MOSFETs, a third constant current source (8C), and first (8D) and second (8E) N-channel load MOSFETs. The sources of the first (8A) and second (8B) P-channel input MOSFETs are connected to the first constant current source (8C), and the drain of the first P-channel input MOSFET (8A) is connected to the drain and gate of the first N-channel load MOSFET (8B) and the gate of the second N-channel load MOSFET (8E). The drain of the second (8B) P-channel input MOSFET is connected to the drain of the second N-channel load MOSFET (8E), the gate of the second P-channel input MOSFET (8B) and the first control conductor (7). The sources of the first (8D) and second (8E) N-channel load MOSFETs are connected to the second supply voltage conductor (GND), and the gate of the first P-channel input MOSFET (8A) is connected to the first reference voltage conductor (6). The second V/I converter (25) includes a differential stage including third (25A) and fourth (25B) N-channel input MOSFETs, a fourth constant current source (25C), and third (25D) and fourth (25E) P-channel load MOSFETs. The sources of the third (25A) and fourth (25B) N-channel input MOSFETs are connected to the fourth constant current source (25C), and the drain of the third N-channel input MOSFET (25A) is connected to the drain of the third P-channel load MOSFET (25D) and the gates of the third (25D) and fourth (25E) P-channel load devices. The sources of the third (25D) and fourth (25E) P-channel load MOSFETs are connected to the first supply voltage conductor (V), and the drain of the fourth P-channel load MOSFET (25E) is connected to the gate of the fourth N-channel input MOSFET (25B) and to the second control conductor (18), the gate of the third N-channel input MOSFET (25A) being connected to the first reference voltage conductor (19). The first feedback circuit includes a first reference current source (23) coupled to the drain (35) of the first current sensing transistor (11) and supplying a current equal to the first predetermined value, a first rectifying circuit (34 or 36) coupled between the drain (35) of the first current sensing transistor (11) and the first control conductor (7). The second feedback circuit includes a second reference current source (21) coupled to the drain (32) of the second current sensing transistor (13) and supplying a current equal to the second predetermined value, a second rectifying circuit (31 or 37) coupled between the drain of the second current sensing transistor (13) and the second control conductor (18). The first rectifying circuit includes a P-channel MOSFET (36) having a gate connected to the first reference conductor (6), a source connected to the drain (35) of the first current sensing transistor (11), and a drain connected to the first control conductor (7). The second rectifying circuit includes a P-channel MOSFET (37) having a gate connected to the second reference conductor (19), a source connected to the drain of the second current sensing transistor (13), and a drain connected to the second control conductor (18).